1. Field of the Invention
The present invention relates to semiconductor memory and in particular to the dynamic operations for non-volatile memory.
2. Description of the Related Art
In conventional non-volatile flash memories, cells are erased on a block level and programmed on a bit level. Therefore, the threshold distributions of erased cells are typically wider than those of the programmed cells, as shown in FIG. 1A. As a result, cell currents of the erased cells may have significant variation, as shown in FIG. 1B. This variation of erased cell currents can be an issue in large arrays where many cells are read or programmed in parallel.
Dynamic Program has been discussed in Prior Art literature, Tatsuya Ishii, et. al., “A 126.6 mm2 AND-type 512 Mb Flash Memory with 1.8V Power Supply,” ISSCC 2001. The memory cell featured in this paper is an assisted-gate AND type cell, which achieves high injection efficiency at low cell currents on the order of tens of nanoAmps. A schematic of a single column of memory cells is shown in FIG. 2. Sub bit-lines SBL[0] & SBL[1] are coupled to voltage sources VBL[0] and VBL[1] through select transistors gated by SG[0] and SG[1], respectively. Program voltages are shown for illustration. Timing of the signals SG[0], SG[1] and selected word line WL[0] are given in FIG. 3. In this approach, program voltages are first applied to the sub bit-lines through select transistors. The select transistors are then de-coupled so that the drain side bit-line is floating. After that, the word line is selected. Because the injection efficiency of the AND cell is high, the charge stored on the drain side bit line (BL) is sufficient to program the cell. The advantage of this dynamic program method is two-fold: (i) unlike typical CHE injection flash memories, DC current is not required during program, and (ii) threshold distribution of the cells programmed by the dynamic program method is tighter, because the amount of charge is fixed.
The Twin MONOS cell is introduced in U.S. Pat. No. 6,255,166 to Ogura et al, assigned to the same assignee as the present invention and herein incorporated by reference in its entirety. In the double-sided selection method, the pair of memory regions 602, 603 under a single control gate (CG) line is selected at the same time. A cross-section of the Twin MONOS cell and the voltage applied during read is given in FIG. 4A. The selected control gate is 802. Control gates 801 and 803 are unselected. The bit line source is 402 and the bit lines for sensing are 401 and 403.
Typical program voltages are shown in FIG. 4B. This type of memory cell has high injection efficiency at even lower voltages than the afore-mentioned AND cell. Because the AND cell stores charge 602, 603 on a floating gate, the coupling ratio is lower. During program, Twin MONOS cells require about 1V on the word gates 901 and 902, 5.5V applied to the selected CG side 802, 3.3V applied to the unselected CG side 801 and 803 to override the underlying memory state, and about 4V to the program side drain 402. Bit lines 401 and 403 provide the floating source, for example.
In the Twin MONOS program method, the low word gate voltage is the main method by which low cell current can be maintained during program. However, variations in word gate threshold voltage within an array can result in a distribution of program currents for the fixed word gate voltage. FIG. 5 shows a plot of cell currents vs. word gate voltage for an array of memory cells. At WG voltage=1V, all cell currents are less than 1 μA.
However, because of the very high injection efficiency, the final VT during program can be highly sensitive depending on array position. In the high density diffusion bit array, bit line resistance can become significant when many rows of memory cells are arrayed together.